MLMI · 2026
ABOUT ME
Stay curious.
Build with purpose.
I am Wei-Kuan Chiang, a Computer Science graduate from Yuan Ze University and an incoming MSc Advanced Computer Science student at The University of Manchester. My research focuses on memory reliability, RTL/FPGA design, edge AI, and intelligent systems. Through an NSTC undergraduate research project, I have worked across the full research pipeline—from test algorithms and hardware architecture to fault injection and on-device FPGA validation.
I also develop real-time AI and software systems in industry, integrating speech interaction, visual perception, streaming, and model inference. These experiences shaped a simple principle behind my work: technology should not only succeed in a paper; it should be deployable, useful, and accountable in the real world.
At Manchester, I plan to deepen my work in machine learning, software engineering, and distributed systems while continuing to turn research ideas into reliable deployed systems.
Machine LearningML SystemsMemory ReliabilityRTL / FPGAEdge AIAI Systems
News
SELECTED UPDATESBeginning the MSc Advanced Computer Science programme at The University of Manchester.
Received the Yuan Ze University Academic Gold Award for outstanding academic and research performance.
Received the Outstanding Paper Award at TANET & NCS 2025.
Completed FPGA validation and PPA analysis for an NSTC project on an optimized March mSR+ memory BIST architecture.
Published research in IEEE Transactions on VLSI Systems.
Publications
Google Scholar ↗IEEE TVLSI · 2025
Enhancing Memory BIST with an Optimized RTL-BIST IP Core: A Low-Power, High-Fault-Coverage Approach
A low-power, high-fault-coverage RTL-BIST IP core designed to improve the efficiency and reliability of embedded memory testing.
ICRAS · 2025
Optimized Memory Reliability Solutions for AI-Driven Automation Systems
A memory-reliability solution for AI-driven automation systems, integrating testing, fault analysis, and hardware validation.
ITAOI · 2025
Design and Application of FPGA-Accelerated Convolutional Neural Networks Based on the PYNQ-Z2 Platform
ITAOI · 2025
Improving YOLO Efficiency in Edge Computing via Hardware Acceleration and Quantization Techniques
TANET & NCS · 2025
Design of an SRAM and OTP Built-In Self-Test Architecture Based on the March C- Enhanced Algorithm
TANET & NCS · 2025 · OUTSTANDING PAPER AWARD
Self-Repairing BISR Memory Architecture Integrating BIST and OTP
A hardware architecture that combines built-in self-test with OTP redundancy information for memory fault localization and self-repair.
Award Paper
Research & Projects
SELECTED GITHUB WORKA focused selection of systems that best represents my work across interpretable machine learning, deployable AI, and human-centred software.
01 · INTERPRETABLE ML
GitHub ↗ECG Stress Analysis
An end-to-end research pipeline for stress classification from WESAD ECG signals: sliding-window HRV extraction, subject-wise cross-validation, Random Forest modelling, SHAP explanations, and a local dashboard that turns model outputs into reviewable reports.
- Python
- Scikit-learn
- SHAP
- Flask
- Ollama
02 · DEPLOYED GENERATIVE AI
Private industry projectAI Wine Cabinet
A voice-first interactive AI installation combining retrieval, speech understanding, response generation, and coordinated multimedia playback for an in-person user experience.
- Generative AI
- Retrieval
- Speech AI
- Interactive System
03 · HUMAN-CENTRED SYSTEM
GitHub ↗Pet Farm — Family Care Platform
A gamified family-care application that turns daily check-ins, shared tasks, reflective prompts, and private photo memories into a collaborative virtual-farm experience.
- Flask
- PostgreSQL
- OAuth
- Gamification
- Privacy-aware Design